Conventionally, a gate driver (a scanning signal line drive circuit) for driving gate lines (scanning signal lines) of a liquid crystal display device is often mounted as an IC (Integrated Circuit) chip in a peripheral portion of a substrate constituting a liquid crystal panel. In recent years, however, formation of a gate driver directly on a substrate is gradually increasing. Such a gate driver is called a “monolithic gate driver” or the like.
In a liquid crystal display device having a monolithic gate driver, a thin film transistor using amorphous silicon (a-Si) (hereinbelow, called a “a-Si TFT”) is employed conventionally as a drive element. However, in recent years, a thin film transistor using microcrystalline silicon (μc-Si) (hereinbelow, called a “μc-Si TFT”) or a thin film transistor using an oxide semiconductor (for example, IGZO) is being employed as a drive element. Hereinafter, a thin film transistor using IGZO will be called an “IGZO TFT”. The μc-Si TFT or IGZO TFT has mobility higher than that of a-Si TFT. Consequently, by employing μc-Si TFT or IGZO TFT as a drive element, reduction in a picture-frame area of the liquid crystal display device and higher definition can be realized.
A display unit in an active matrix-type liquid crystal display device includes a plurality of source lines (video signal lines), a plurality of gate lines, and a plurality of pixel formation portions provided at the respective intersections of the plurality of source lines and the plurality of gate lines. The pixel formation portions are disposed in a matrix, thereby forming a pixel array. Each of the pixel formation portions includes a thin film transistor (switching element) having a gate terminal connected to a gate line passing a corresponding intersection and a source terminal connected to a source line passing the intersection, and a pixel capacitance for holding a pixel voltage value. The active matrix-type liquid crystal display device is also provided with the above-described gate driver and a source driver (video signal line drive circuit) for driving source lines.
A video signal indicative of a pixel voltage value is transmitted by a source line. However, video signals indicative of pixel voltage values of a plurality of rows cannot be transmitted by each source line at once (simultaneously). Due to this, the video signals are sequentially written (charged) row by row to the pixel capacitances in the above-described pixel formation portions disposed in a matrix. Consequently, the gate driver is configured by a shift register including a plurality of stages so that the plurality of gate lines are sequentially selected for a predetermined period. Each of the stages of the shift register is a bistable circuit that is in either one of two states (a first state and a second state) at each time point, and that outputs, as a scanning signal, a signal (hereinbelow, called a “state signal”) indicating this state. By outputting active scanning signals sequentially from a plurality of bistable circuits in the shift register, the video signals are sequentially written to the pixel capacitances row by row as described above.
A bistable circuit in a conventional gate driver is configured, for example, as illustrated in FIG. 32. Such a bistable circuit is disclosed in, for example, Patent Document 1. It should be noted that transistors M3 and M7 in FIG. 32 may have a multigate configuration as disclosed in Patent Document 1. In the following, the bistable circuit illustrated in FIG. 32 will be called a “first conventional example”. In the first conventional example, when a scanning signal GOUT(i−1) (set signal S) transmitted from the preceding stage becomes the high level, the transistor M3 enters an on state, so that the potential of a second node N2 becomes the low level. Consequently, transistors M5 and M6 enter an off state. Therefore, by the scanning signal GOUT(i−1) becoming the high level, the potential of the first node N1 becomes the high level, and a capacitor C1 is charged. In this state, the potential of the clock signal CK appears in the gate line. Consequently, after the scanning signal GOUT(i−1) sent from the preceding stage becomes the high level in each bistable circuit, the potential of the clock signal CK to be supplied to the bistable circuit is set to the high level, so that active scanning signals are sequentially output from a plurality of bistable circuits in the shift register. Thus, a plurality of gate lines are driven sequentially one by one. In each of the bistable circuits, in a period (a “normal operation period” which will be described later) other than a period in which an operation for outputting an active scanning signal is performed, the potential of the second node N2 is maintained at the high level so that the potential of the first node N1 is maintained at the low level.
As described above, in the normal operation period, the potential of the second node N2 has to be maintained at the high level so that the potential of the first node N1 is maintained at the low level. Consequently, in the normal operation period, a high-level potential (the potential of the second node N2) is always applied to the gate terminals of the transistors M5 and M6. Since a period in which operation for outputting an active scanning signal is performed is small in each vertical scanning period, a substantially DC potential is applied to the gate terminals of the transistors M5 and M6. As a result, the threshold shift which occurs in the transistors M5 and M6 becomes large, and it causes deterioration in the reliability of the transistors.
In relation to the present invention, Patent Document 2 discloses a gate driver including, as illustrated in FIG. 33, a plurality of bistable circuits each configured by an input unit 920, a pull-up driving unit 930, a pull-down driving unit 940, and an output unit 950. In the following, the bistable circuit illustrated in FIG. 33 will be called a “second conventional example”. The input unit 920 in the second conventional example is constituted by a transistor T1, the pull-up driving unit 930 is constituted by transistors T9 and T10, the pull-down driving unit 940 is constituted by transistors T3, T4, T7, T8, and T11, and the output unit 950 is constituted by transistors T1, T5, and T6 and a capacitor C1. A second node is connected to the gate terminals of the transistors T4 and T5. The transistors T4 and T5 correspond to the above-described transistors M5 and M6, respectively. To the bistable circuit, two-phase clock signals CK1 and CK2 (duty ratio 1/4) are supplied. The clock signal CK1 is supplied to the drain terminal of the transistor T1, the gate terminal and the drain terminal of the transistor T9, and the gate terminal of the transistor T11. The clock signal CK1 is also supplied to the gate terminal of the transistor T4 and the gate terminal of the transistor T5 via the transistor T9. The clock signal CK2 is supplied to the gate terminal of the transistor T8 and the gate terminal and the drain terminal of the transistor T10. The clock signal CK2 is also supplied to the gate terminal of the transistor T6 via the transistor T10.
In the second conventional example, in a manner similar to the first conventional example, the potential of the second node N2 becomes the low level in the period in which the operation for outputting an active scanning signal is performed. On the other hand, in the normal operation period, the potential of the second node N2 becomes the high level when the clock signal CK1 becomes the high level, and becomes the low level when the clock signal CK2 becomes the high level. Therefore, potential whose duty ratio is substantially 1/2 is supplied to the gate terminals of the transistors T4 and T5 to which the second node N2 is connected. As a result, the threshold shift which occurs in the transistors T4 and T5 can be suppressed, so that the reliability of the transistors can be increased.